EFM32G-DK3550【PDF 51/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

? provide a contiguous area of system memory that the controller and host processor can access

? have a base address that is an integer multiple of the total size of the channel control data structure.

Figure 8.6 (p. 51) shows the memory that the controller requires for the channel control data structure,

when all 8 channels and the optional alternate data structure are in use.

Figure 8.6. Memory map for 8 channels, including the alternate data structure

Alternate data structure

Prim ary data structure

Alternate_Ch_7

Alternate_Ch_6

Alternate_Ch_5

Alternate_Ch_4

Alternate_Ch_3

Alternate_Ch_2

Alternate_Ch_1

Alternate_Ch_0

0x100

0x0F0

0x0E0

0x0D0

0x0C0

0x0B0

0x0A0

0x090

0x080

Prim ary_Ch_7

Prim ary_Ch_6

Prim ary_Ch_5

Prim ary_Ch_4

Prim ary_Ch_3

Prim ary_Ch_2

Prim ary_Ch_1

Prim ary_Ch_0

0x080

0x070

0x060

0x050

0x040

0x030

0x020

0x010

0x000

Unused

Control

Destination End Pointer

Source End Pointer

0x00C

0x008

0x004

0x000

This structure in Figure 8.6 (p. 51) uses 256 bytes of system memory. The controller uses the lower

8 address bits to enable it to access all of the elements in the structure and therefore the base address

must be at 0xXXXXXX00 .

You can configure the base address for the primary data structure by writing the appropriate value in

the DMA_CTRLBASE register.

You do not need to set aside the full 256 bytes if not all 8 channels are used or not all alternate descriptors

are used. If e.g. only 4 channels are used and they only need the primary descriptors, then only 64 bytes

need be set aside.

Table 8.6 (p. 51) lists the address bits that the controller uses when it accesses the elements of the

channel control data structure.

Table 8.6. Address bit settings for the channel control data structure

Address bits

[7]

A

[6]

C[2]

[5]

C[1]

[4]

C[0]

[3:0]

0x0, 0x4, or 0x8

Where:

A

Selects one of the channel control data structures:

A=0

A=1

Selects the primary data structure.

Selects the alternate data structure.

C[2:0]

Address[3:0]

Selects the DMA channel.

Selects one of the control elements:

0x0

0x4

0x8

0xC

Selects the source data end pointer.

Selects the destination data end pointer.

Selects the control data configuration.

The controller does not access this address location. If required, you can

enable the host processor to use this memory location as system memory.

Note

It is not necessary for you to calculate the base address of the alternate data structure

because the DMA_ALTCTRLBASE register provides this information.

Figure 8.7 (p. 52) shows a detailed memory map of the descriptor structure.

2011-04-12 - d0001_Rev1.10

51

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